Getting errors to catch themselves - self-testing of VLSI circuits with built-in hardware

• Published in: IEEE transactions on instrumentation and measurement Vol. 54; no. 3; pp. 941 - 955
• Main Author: Das, S.R.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.06.2005; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Automatic testing; Built-in self-test; Built-in self-test (BIST); Chips; Circuit testing; Circuits; Complex systems; cores-based system-on-chip (SOC); Digital systems; Electronic equipment testing; Electronics industry; Hardware; Integrated circuit reliability; Integrated circuits; Methodology; module under test (MUT); scan test; signature analysis; space compaction; System testing; Testability; time compaction; Very large scale integration
• ISSN: 0018-9456; 1557-9662
• DOI: 10.1109/TIM.2005.847352

As the electronics industry continues to grow, technology feature sizes continue to decrease, and complex systems and levels of integration continue to increase, the need for better and more effective methods of testing to ensure reliable operations of chips, the mainstay of today's all digital systems, is being increasingly felt. One obvious way to significantly improve the testability of digital VLSI circuits and save testing time is to use built-in self-testing (BIST), where the basic idea is to have the chip test itself. BIST is a design methodology that combines the concepts of built-in test (BIT) and self-test (ST) in one, termed BIST. This technique generates test patterns and evaluates test responses inside the chip system, and has been widely used in many commercial VLSI products with appreciable success. The subject paper endeavors to present a comprehensive overview of the general methodology of BIST from its various perspectives, and in the sequel attempts to relate its significance in the particular context of modern embedded cores-based system-on-chip (SOC) technology.