Cache Hierarchy and Memory Subsystem of the AMD Opteron Processor

The 12-core AMD Opteron processor, code-named "Magny Cours," combines advances in silicon, packaging, interconnect, cache coherence protocol, and server architecture to increase the compute density of high-volume commodity 2P/4P blade servers while operating within the same power envelope...

Full description

Saved in:
Bibliographic Details
Published inIEEE MICRO Vol. 30; no. 2; pp. 16 - 29
Main Authors Conway, Pat, Kalyanasundharam, Nathan, Donley, Gregg, Lepak, Kevin, Hughes, Bill
Format Journal Article
LanguageEnglish
Published Los Alamitos IEEE 01.03.2010
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects
Bandwidth
blade server
Blades
Broadcasting
Cache
cache directory
Coherence
Computer architecture
Computer memory
Delay
Density
Filters
Hierarchies
High tech industries
HyperTransport3 technology
memory hierarchy
Microprocessors
multiprocessor
Packaging
power envelopes
probe filter
Probes
processor
Protocols
Servers
Silicon
system interconnect
x86-64
Online AccessGet full text

Cover

More Information
Summary:The 12-core AMD Opteron processor, code-named "Magny Cours," combines advances in silicon, packaging, interconnect, cache coherence protocol, and server architecture to increase the compute density of high-volume commodity 2P/4P blade servers while operating within the same power envelope as earlier-generation AMD Opteron processors. A key enabling feature, the probe filter, reduces both the bandwidth overhead of traditional broadcast-based coherence and memory latency.
Bibliography:ObjectType-Article-1
SourceType-Scholarly Journals-1
ObjectType-Feature-2
content type line 23
ISSN:0272-1732
1937-4143
DOI:10.1109/MM.2010.31