Modelling and verification of delay-insensitive circuits using CCS and the Concurrency Workbench

The modelling of delay-insensitive asynchronous circuits in the process calculus CCS is addressed. MUST-testing (rather than bisimulation) is found to support verification both of the property of delay-insensitivity and of design by stepwise refinement. Automated verification is possible with a well...

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Bibliographic Details
Published inInformation processing letters Vol. 89; no. 6; pp. 293 - 296
Main Authors Kapoor, Hemangee K., Josephs, Mark B.
Format Journal Article
LanguageEnglish
Published Amsterdam Elsevier B.V 31.03.2004
Elsevier Science
Elsevier Sequoia S.A
Subjects
Algorithmics. Computability. Computer arithmetics
Applied sciences
Asynchronous logic
Calculus
Circuits
Computer science; control theory; systems
Exact sciences and technology
Formal methods
Formal verification
Mathematical models
Programming languages
Software
Software engineering
Specification languages
Studies
Theoretical computing
Specification languages
Formal methods
Formal verification
Asynchronous logic
Specification language
Formal method
Computer theory
Concurrency
Information processing
Verification
AND circuit
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Summary:The modelling of delay-insensitive asynchronous circuits in the process calculus CCS is addressed. MUST-testing (rather than bisimulation) is found to support verification both of the property of delay-insensitivity and of design by stepwise refinement. Automated verification is possible with a well-known tool, the Edinburgh Concurrency Workbench.
ISSN:0020-0190
1872-6119
DOI:10.1016/j.ipl.2003.12.007