Design of CMOS Transistors to Maximize Circuit FOM Using a Coupled Process and Mixed-Mode Simulation Methodology

• Published in: IEEE electron device letters Vol. 27; no. 10; pp. 863 - 865
• Main Authors: Venugopal, R., Chakravarthi, S., Chidambaram, P.R.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.10.2006; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Capacitance; Circuit; Circuit design; Circuit optimization; Circuit simulation; Circuits; CMOS; CMOS process; Coupling circuits; Design. Technologies. Operation analysis. Testing; Devices; Electric, optical and optoelectronic circuits; Electronic equipment and fabrication. Passive components, printed wiring boards, connectics; Electronics; Electrostatics; Exact sciences and technology; figure of merit (FOM); Integrated circuits; Inverters; Leakage current; MOS devices; Optimization; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Semiconductor process modeling; Simulation; Theoretical study. Circuits analysis and design; Threshold voltage; transistor scaling; Transistors; Performance evaluation; Inverter; Circuit simulation; Short channel; Transistor circuits; Circuit; figure of merit (FOM); NOR circuit; Switching; Logic circuit; Complementary MOS transistor; Capacitance; Delay time; transistor scaling; CMOS integrated circuits; Barrier height; Simulator; Figure of merit
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/LED.2006.882565

Calibrated process and device CMOS modules were integrated into a mixed-mode simulation setup to study the circuit figure of merit (FOM). Switching delay from typical two-input NAND, two-input NOR, and inverter circuits built and simulated in the device simulator Dessis, including both intra and intercell capacitances and resistances show strong dependence on the drain-induced barrier lowering and associated short-channel electrostatics. The analysis presented in this letter identifies, for a given set of leakage and process constraints, an optimal gate length (L g ) that maximizes circuit FOM. The analysis also highlights, for the first time, that the optimal L g for maximizing circuit FOM is much longer than that required for maximizing the device performance. The optimal L g for maximum circuit FOM is determined by a complex tradeoff between reduced capacitance, increased short-channel effect, and reduced mobility