ECG Authentication Hardware Design With Low-Power Signal Processing and Neural Network Optimization With Low Precision and Structured Compression

• Published in: IEEE transactions on biomedical circuits and systems Vol. 14; no. 2; pp. 198 - 208
• Main Authors: Cherupally, Sai Kiran, Yin, Shihui, Kadetotad, Deepak, Srivastava, Gaurav, Bae, Chisung, Kim, Sang Joon, Seo, Jae-sun
• Format: Journal Article
• Language: English
• Published: United States IEEE 01.04.2020; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Artificial neural networks; Authentication; Biometrics; Biometry; CMOS; Compression; Cost function; DNN compression; ECG authentication; EKG; Electrocardiography; Electrocardiography - instrumentation; Feature extraction; fixed-coefficient filtering; Hardware; Humans; Microprocessors; neural network optimization; Neural networks; Neural Networks, Computer; Neurons; Optimization; Power consumption; Power management; Signal processing; Signal Processing, Computer-Assisted - instrumentation; Smartphones; Smartwatches; structured sparsity; Tablet computers; Wearable Electronic Devices; Wearable technology
• ISSN: 1932-4545; 1940-9990
• DOI: 10.1109/TBCAS.2020.2974387

Biometrics such as facial features, fingerprint, and iris are being used increasingly in modern authentication systems. These methods are now popular and have found their way into many portable electronics such as smartphones, tablets, and laptops. Furthermore, the use of biometrics enables secure access to private medical data, now collected in wearable devices such as smartwatches. In this work, we present an accurate low-power device authentication system that employs electrocardiogram (ECG) signals as the biometric modality. The proposed ECG processor consists of front-end signal processing of ECG signals and back-end neural networks (NNs) for accurate authentication. The NNs are trained using a cost function that minimizes intra-individual distance over time and maximizes inter-individual distance. Efficient low-power hardware was implemented by using fixed coefficients for ECG signal pre-processing and by using joint optimization of low-precision and structured sparsity for the NNs. We implemented two instances of ECG authentication hardware with 4X and 8X structurally-compressed NNs in 65 nm LP CMOS, which consume low power of 62.37 μW and 75.41 μW for real-time ECG authentication with alow equal error rate of 1.36% and 1.21%, respectively, for a large 741-subject in-house ECG database. The hardware was evaluated at 10 kHz clock frequency and 1.2 V voltage supply.