A Wireless Headstage System Based on Neural-Recording Chip Featuring 315 nW Kickback-Reduction SAR ADC

• Published in: IEEE transactions on biomedical circuits and systems Vol. 17; no. 1; pp. 105 - 115
• Main Authors: Zhang, Yunshan, Yang, Changgui, Sun, Junhong, Li, Zhuhao, Gao, Huan, Luo, Yuxuan, Xu, Kedi, Pan, Gang, Zhao, Bo
• Format: Journal Article
• Language: English
• Published: United States IEEE 01.02.2023; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Analog to digital converters; Analog-digital conversion; analog-to-digital converter (ADC); Animals; Capacitors; Equipment Design; Head; IP networks; kickback noise; Kickbacks; low power; Male; Movement disorders; Neural recording; Neurodegenerative diseases; Noise levels; Parkinson's disease; Power consumption; Power management; Rats; Rats, Sprague-Dawley; Recording; Recording instruments; Registers; Signal transmission; Transistors; Wireless communication; wireless headstage; Wireless Technology
• ISSN: 1932-4545; 1940-9990; 1940-9990
• DOI: 10.1109/TBCAS.2022.3224387

Wireless neural-recording instruments eliminate the bulky cables in multi-channel signal transmission, while the system size should be reduced to mitigate the impact on freely-moving animals. As the battery usually dominates the system size, the neural-recording chip should be low power to minimize the battery in long-termly monitoring. In general, a neural-recording chip consists of an analog front end (AFE) and an 8 bit <inline-formula><tex-math notation="LaTeX">-</tex-math></inline-formula>10 bit analog-to-digital converter (ADC), while it's challenging to design an ADC with an 8<inline-formula><tex-math notation="LaTeX">-</tex-math></inline-formula>10 effective number of bits (ENOB) and sub-<inline-formula><tex-math notation="LaTeX">\mu</tex-math></inline-formula> W power consumption due to the kickback noise. In this work, we propose a kickback-reduction technique for a successive-approximation-register (SAR) ADC based on neural-recording chip. Fabricated in 65 nm CMOS process, the proposed technique reduce the ADC power to 315 nW, resulting in an 8-channel neural-recording chip with 249 <inline-formula><tex-math notation="LaTeX">\mu</tex-math></inline-formula>W in total. Measured results show that the chip achieves an ADC ENOB of 9.73 bits, as well as an AFE gain of 43.3 dB and input-referred noise (IRN) of 9.68 <inline-formula><tex-math notation="LaTeX">\mu V_{rms}</tex-math></inline-formula> in a bandwidth of 0.9 Hz<inline-formula><tex-math notation="LaTeX">-</tex-math></inline-formula>7.2 kHz. Combined with a BLE chip and a PCB antenna, the chip is implemented into a 2.6 g wireless headstage system (w/o battery), and an in-vivo demonstration is conducted on a male Sprague-Dawley rat with Parkinson's disease. The headstage system transfers the in-vivo neural signals to a commodity smartphone through BLE, and the miniature size induces little impact on freely-moving activities.