Fundamentals of silicon material properties for successful exploitation of strain engineering in modern CMOS manufacturing

• Published in: IEEE transactions on electron devices Vol. 53; no. 5; pp. 944 - 964
• Main Authors: Chidambaram, P.R., Bowen, C., Chakravarthi, S., Machala, C., Wise, R.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.05.2006; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Chemical diffusion; CMOS; defect; Defects; device; diffusion; dislocation; electron; Germanium alloys; High-temperature techniques; hole; intrinsic; isolation; layout; metrology; mobility; MOSFETs; NMOS; PMOS; process; Semiconductor device manufacture; Semiconductor devices; Semiconductors; SiGe; Silicon; Silicon alloys; Strain; stress; temperature; Transistors
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2006.872912

Semiconductor industry has increasingly resorted to strain as a means of realizing the required node-to-node transistor performance improvements. Straining silicon fundamentally changes the mechanical, electrical (band structure and mobility), and chemical (diffusion and activation) properties. As silicon is strained and subjected to high-temperature thermal processing, it undergoes mechanical deformations that create defects, which may significantly limit yield. Engineers have to manipulate these properties of silicon to balance the performance gains against defect generation. This paper will elucidate the current understanding and ongoing published efforts on all these critical properties in bulk strained silicon. The manifestation of these properties in CMOS transistor performance and designs that successfully harness strain is reviewed in the last section. Current manufacturable strained-silicon technologies are reviewed with particular emphasis on scalability. A detailed case study on recessed silicon germanium transistors illustrates the application of the fundamentals to optimal transistor design.