A Compact Physical Model for Yield Under Gate Length and Body Thickness Variations in Nanoscale Double-Gate CMOS

• Published in: IEEE transactions on electron devices Vol. 53; no. 9; pp. 2151 - 2159
• Main Authors: Ananthan, H., Roy, K.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.09.2006; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Circuit design; Computer simulation; Design. Technologies. Operation analysis. Testing; Devices; Double-gate (DG); Electronics; Exact sciences and technology; FinFET; Gates (circuits); Integrated circuits; leakage distribution; Logic gates; Mathematical model; Mathematical models; Monte Carlo methods; MOSFET; multiple gate; Nanoscale devices; Nanostructure; process variations; Quantum confinement; Semiconductor device modeling; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Silicon-on-insulator; Threshold voltage; threshold voltage distribution; Transistors; tri-gate; Voltage threshold; Estimation error; Monte Carlo method; MOSFET; Confinement; Circuit design; Error estimation; multiple gate; FinFET; tri-gate; Poisson equation; Dual gate transistor; Compact design; Index Terms-Double-gate (DG); Schrödinger equation; Self aligned technology; Silicon on insulator technology; threshold voltage distribution; leakage distribution; Complementary MOS technology; process variations; Numerical simulation
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2006.880365

Double-gate (DG) CMOS is projected to replace classical bulk and silicon-on-insulator technologies around the 32-nm node. Predicting the impact of process variations on yield for these devices is necessary at an early stage of the design cycle to enable optimal technology and circuit design choices. This paper presents a compact physical model for DG leakage and threshold voltage distribution due to gate length L and body thickness t si variations, both for single devices and multiple-device stacks. The model is derived directly from the solution of Poisson and Schrodinger equations and thus captures the effect of unique DG phenomena such as volume inversion and quantum confinement. The model is verified for devices at the end of the scaling roadmap (L=13nm, t si =3nm), with the yield estimation error less than 3% compared to the Monte Carlo simulation for a 3sigma variation of as much as 20% of the nominal process parameters