A mixed-mode ESD protection circuit simulation-design methodology

On-chip electrostatic discharge (ESD) protection design becomes a major design challenge as IC technologies continue to migrate into very-deep-submicron (VDSM) regime. However, trial-and-error approaches still dominate in ESD protection circuit design. This paper discusses a new mixed-mode ESD prote...

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Bibliographic Details
Published inIEEE journal of solid-state circuits Vol. 38; no. 6; pp. 995 - 1006
Main Authors Haigang Feng, Guang Chen, Rouying Zhan, Qiong Wu, Guan, X., Haolu Xie, Wang, A.Z.H., Gafiteanu, R.
Format Journal Article
LanguageEnglish
Published New York IEEE 01.06.2003
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects
Circuit design
Circuit simulation
Circuit synthesis
Circuits
CMOS
CMOS process
Coupling circuits
Design methodology
Electrostatic discharge
Electrostatic discharges
Electrothermal effects
Equations
Joining
Mathematical analysis
Methodology
Predictive models
Protection
Simulation
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Summary:On-chip electrostatic discharge (ESD) protection design becomes a major design challenge as IC technologies continue to migrate into very-deep-submicron (VDSM) regime. However, trial-and-error approaches still dominate in ESD protection circuit design. This paper discusses a new mixed-mode ESD protection simulation-design methodology, aiming to design prediction, which involves multiple-level coupling in ESD protection simulation by solving complex electrothermal equations self-consistently at process, device, and circuit levels in a coupled fashion to investigate ESD protection circuit details without any pre-assumption. Practical ESD protection design examples, implemented in commercial 0.18/0.35-/spl mu/m CMOS and BiCMOS processes, are presented.
Bibliography:ObjectType-Article-2
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ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2003.811978