A Scalable Multicore Architecture With Heterogeneous Memory Structures for Dynamic Neuromorphic Asynchronous Processors (DYNAPs)

• Published in: IEEE transactions on biomedical circuits and systems Vol. 12; no. 1; pp. 106 - 122
• Main Authors: Moradi, Saber, Ning Qiao, Stefanini, Fabio, Indiveri, Giacomo
• Format: Journal Article
• Language: English
• Published: United States IEEE 01.02.2018; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Analog circuits; Artificial neural networks; Asynchronous; Circuits; circuits and systems; Computer memory; Digital electronics; Electronic systems; Latency; Memory management; Microprocessors; Models, Theoretical; Neural networks; Neural Networks (Computer); neuromorphic computing; Neuromorphics; Neurons; Power consumption; Prototypes; Routing; routing architectures; Theoretical analysis; Traffic management; Visual pathways; Visual stimuli
• ISSN: 1932-4545; 1940-9990; 1940-9990
• DOI: 10.1109/TBCAS.2017.2759700

Neuromorphic computing systems comprise networks of neurons that use asynchronous events for both computation and communication. This type of representation offers several advantages in terms of bandwidth and power consumption in neuromorphic electronic systems. However, managing the traffic of asynchronous events in large scale systems is a daunting task, both in terms of circuit complexity and memory requirements. Here, we present a novel routing methodology that employs both hierarchical and mesh routing strategies and combines heterogeneous memory structures for minimizing both memory requirements and latency, while maximizing programming flexibility to support a wide range of event-based neural network architectures, through parameter configuration. We validated the proposed scheme in a prototype multicore neuromorphic processor chip that employs hybrid analog/digital circuits for emulating synapse and neuron dynamics together with asynchronous digital circuits for managing the address-event traffic. We present a theoretical analysis of the proposed connectivity scheme, describe the methods and circuits used to implement such scheme, and characterize the prototype chip. Finally, we demonstrate the use of the neuromorphic processor with a convolutional neural network for the real-time classification of visual symbols being flashed to a dynamic vision sensor (DVS) at high speed.