Design of a pipelined 8-bit-serial single-flux-quantum microprocessor with multiple ALUs

• Published in: Superconductor science & technology Vol. 19; no. 5; pp. S344 - S349
• Main Authors: Tanaka, M, Kawamoto, T, Yamanashi, Y, Kamiya, Y, Akimoto, A, Fujiwara, K, Fujimaki, A, Yoshikawa, N, Terai, H, Yorozu, S
• Format: Journal Article
• Language: English
• Published: IOP Publishing 01.05.2006
• ISSN: 0953-2048; 1361-6668
• DOI: 10.1088/0953-2048/19/5/S38

We have designed a pipelined 8-bit-serial single-flux-quantum microprocessor with multiple ALUs, called CORE1 beta. In the CORE1 beta, two ALUs connected in cascade enable us to perform two calculations on serial data using a register-to-register instruction, to enhance the peak performance. In addition, we have introduced pipelining to boost the performance. Although the pipelining is a difficult technique that requires a complex design in the datapath, we have implemented a simplified pipeline with seven stages by using two techniques. One is the separation of clock signals for pipelining and bit processing, and the other is the introduction of new buffers driven by independent clock signals for reading and writing flexibly in order to ease the difficulty in timing design between the register file and the ALUs. According to the logic simulation, the peak performance of the designed microprocessor is estimated to be 1500 million operations per second with a power consumption of 3.3 mW. We have fabricated the CORE1 beta chip by using the NEC 2.5 kA cm-2 niobium standard process, and confirmed the correct operations of several instructions using high-speed clocks.