Checkpoint processing and recovery: an efficient, scalable alternative to reorder buffers

Processors require a combination of large instruction windows and high clock frequency to achieve high performance. Traditional processors use reorder buffers, but these structures do not scale efficiently as window size increases. A new technique, checkpoint processing and recovery, offers an effic...

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Bibliographic Details
Published inIEEE MICRO Vol. 23; no. 6; pp. 11 - 19
Main Authors Akkary, H., Rajwar, R., Srinivasan, S.T.
Format Journal Article
LanguageEnglish
Published Los Alamitos IEEE 01.11.2003
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects
Buffers
Clocks
Decoding
Delay
Hazards
Microarchitecture
Microprocessors
Out of order
Performance evaluation
Pipelines
Processors
Recovery
Registers
Retirement
Scalability
Tail
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Summary:Processors require a combination of large instruction windows and high clock frequency to achieve high performance. Traditional processors use reorder buffers, but these structures do not scale efficiently as window size increases. A new technique, checkpoint processing and recovery, offers an efficient means of increasing the instruction window size without requiring large, cycle-critical structures, and provides a promising microarchitecture for future high-performance processors.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
ISSN:0272-1732
1937-4143
DOI:10.1109/MM.2003.1261382