A new CMOS comparator robust to process and temperature variations for SAR ADC converters

• Published in: Analog integrated circuits and signal processing Vol. 90; no. 2; pp. 301 - 308
• Main Authors: de La Fuente-Cortes, Gisela, Espinosa Flores-Verdad, Guillermo, Gonzalez-Diaz, Victor R., Diaz-Mendez, A.
• Format: Journal Article
• Language: English
• Published: New York Springer US 01.02.2017; Springer Nature B.V
• Subjects: Analog to digital converters; Biomedical materials; Circuits and Systems; CMOS; Comparators; Corners; Electrical Engineering; Engineering; Mathematical analysis; Noise levels; Power consumption; Robustness; Signal to noise ratio; Signal,Image and Speech Processing; Process and temperature variations; ADC SAR; Analog comparator; Robust design
• ISSN: 0925-1030; 1573-1979
• DOI: 10.1007/s10470-016-0916-9

This paper presents a novel comparator being robust to temperature and process variations. The new comparator is confronted to a conventional topology used in most of the Successive Approximations Analog to Digital Converters (SAR ADCs) for biomedical applications. To verify the benefits of the new comparator, it was designed on a CMOS 65 nm process and characterized with post layout simulations under conditions of process and temperature fluctuations. With the proposed circuit, a SAR ADC exhibits 83.11 dB of Signal to Noise Ratio at 1.28 MS/s and 375 μ W of power consumption. The PT variations for critical corners are less than 0.58 bits.