Modeling and Analysis of On-Chip Single and H-tree Distributed RLC Interconnects

• Published in: Circuits, systems, and signal processing Vol. 35; no. 9; pp. 3049 - 3065
• Main Authors: Kavicharan, Mummaneni, Murthy, Nukala Suryanarayana, Rao, Nistala Bheema, Prathima, Addanki
• Format: Journal Article
• Language: English
• Published: New York Springer US 01.09.2016; Springer Nature B.V
• Subjects: Approximation; Circuits and Systems; Delay; Electrical Engineering; Electronics and Microelectronics; Engineering; Errors; Inductance; Instrumentation; Interconnections; Mathematical analysis; Mathematical models; Model accuracy; Model reduction; Ramps; Rational functions; Signal,Image and Speech Processing; Transfer functions; Tungsten; RLC interconnects; Distributed H-tree network; S & S method; Ramp input; MPTA method; Transient analysis; Delay
• ISSN: 0278-081X; 1531-5878
• DOI: 10.1007/s00034-015-0188-0

This paper presents novel methods for modeling and analysis of on-chip Single and H-tree distributed resistance inductance capacitance interconnects. The matrix pade-type approximation and scaling and squaring methods are employed for the numerical estimation of delay in single interconnect, and H-tree interconnects. The proposed models, which are based on these methods, provide rational function approximation for obtaining a passive interconnect model. Multiple single input single output model approximated transfer functions are developed for H-tree interconnects structure. With the equivalent reduced order lossy interconnect transfer functions, finite ramp responses are obtained, and line delay is estimated for various line lengths, input ramp rise times, source resistances, parasitic capacitances and load capacitances. In order to demonstrate the accuracy of proposed models, the estimated 50 % delay values are compared with the standard HSPICE W-element model and are found to be in good agreement. The proposed models worst case 50 % delay errors of single interconnect are 0.27 and 0.24 % respectively, while the worst case 50 % delay errors of H-tree structure are 5.73 and 3.94 % respectively.