Test Data Compression and Power Reduction Using Similarity Based Reordering Technique for Wireless Systems

• Published in: Wireless personal communications Vol. 90; no. 2; pp. 713 - 728
• Main Authors: HariKumar, R., Manjurathi, B.
• Format: Journal Article
• Language: English
• Published: New York Springer US 01.09.2016; Springer Nature B.V
• Subjects: Coding; Communications Engineering; Compression tests; Computer Communication Networks; Data compression; Design engineering; Engineering; Networks; Power consumption; Preprocessing; Product development; Reduction; Signal,Image and Speech Processing; Similarity; Switching; System on chip; Similarity based test vector reordering; Test data compression; Difference vector; Modified Golomb Code; Test power reduction; Don’t care fill
• ISSN: 0929-6212; 1572-834X
• DOI: 10.1007/s11277-016-3196-x

System-on-Chip is the major challenge for both design and testing engineers due to its increase in power consumption. The system consumes more power in test mode than the normal mode due to the switching activity that takes place between test data. Similarly, in test mode the volume of test data used is very high when compared to normal mode. This paper presents a novel test data compression approach which simultaneously reduces test volume, test power consumption with less decoder complexity. A test data compression when combined with efficient preprocessing such as filling and reordering of test patterns leads to efficient compression and power reduction. These are some preprocessing steps prior to the compression coding, affects the power. In this paper, the preprocessing steps proposed are column wise bit filling; Similarity based test vector reordering, difference vector techniques. This approach with Modified Golomb coding is proposed to improve the compression as well as to reduce the scan in peak power and average power. This approach efficiently decreases the switching activity and also very simple method to combine with run length based coding. The Power reduction is very efficient by this proposed method compared to other preprocessing methods. A careful analysis of bit filling is proposed that leads to significant reduction in peak and average power. Similarity based test vector reordering technique is also proposed to reorder the test data for reducing the switching activity that takes place in test data and reduces the power consumption. The difference vector is applied which leads to increase in the run length of 0s.The modified Golomb algorithm proposed next can efficiently compress the test set that composed of both 0s and 1s.The decompression architecture is also presented in the paper. Experimental results on ISCAS’89 benchmark circuits show that the proposed approach efficiently reduces the volume of test data and the peak, average power consumption.