A functional 41-stage ring oscillator using scaled FinFET devices with 25-nm gate lengths and 10-nm fin widths applicable for the 45-nm CMOS node

• Published in: IEEE electron device letters Vol. 25; no. 8; pp. 568 - 570
• Main Authors: Collaert, N., Dixit, A., Goodwin, M., Anil, K.G., Rooyackers, R., Degroote, B., Leunissen, L.H.A., Veloso, A., Jonckheere, R., De Meyer, K., Jurczak, M., Biesemans, S.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.08.2004; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Barriers; CMOS; CMOS technology; Design optimization; Devices; Digital circuits; Etching; FinFETs; Fins; Gates; Implants; Leakage; MOSFET circuits; Oscillators; Ring oscillators; Scanning electron microscopy
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/LED.2004.831585

We have fabricated a functional FinFET ring oscillator with a physical gate length of 25 nm and a fin width of 10 nm, the smallest ever reported. We demonstrate that these narrow (W/sub fin/ = 10 nm) and tall (H/sub fin/ = 60 - 80 nm) fins can be reliably etched with controlled profiles and that they are required to keep the short-channel effects under control, resulting in drain-induced barrier leakage characteristics of 45 mV/V at V DD = 1 V and L/sub g/ = 25 nm for the nFET. For these ultrathin (10 nm) fins, we have succeeded in properly setting the V T at 0.2 V without the use of metal gates. In addition to ring oscillators, we also have obtained excellent pFET FinFET devices at wider fin widths (W/sub fin/ = 65 nm) with I/sub dsat/ = 380 μA/μm at I/sub off/ = 60 nA/μm and V DD = -1.2 V.