Novel ultrahigh-density flash memory with a stacked-surrounding gate transistor (S-SGT) structured cell

• Published in: IEEE transactions on electron devices Vol. 50; no. 4; pp. 945 - 951
• Main Authors: Endoh, T., Kinoshita, K., Tanigami, T., Wada, Y., Sato, K., Yamada, K., Yokoyama, T., Takeuchi, N., Tanaka, K., Awaya, N., Sakiyama, K., Masuoka, F.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.04.2003; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Cellular logic arrays; Tunneling; Very-large-scale integration
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2003.809429

In order to overcome the limitation of cell area of 4F/sup 2/ per bit in conventional NAND flash memory cells, stacked-surrounding gate transistor (S-SGT) structured cell is proposed. This newly structured cell achieves a cell area of 4F/sup 2//N per bit, where N is the number of stacked memory cells in one silicon pillar, without using multibit per memory cell technology. The S-SGT structured cell consisting of two stacked memory cells in one silicon pillar achieves a cell area per bit of less than 50% of the smallest reported NAND structured cell. The novel S-SGT structured cells are fabricated by vertical self-aligned processes using a 0.2 /spl mu/m design rule. The S-SGT structured cell can be programmed and erased by uniform injection and uniform emission of Fowler-Nordheim (F-N) tunneling electrons over the whole channel area of the memory cell, respectively, which is the same program and erase mechanism as in conventional NAND structured cell. This high performance S-SGT structured cell is applicable to high-density nonvolatile memories for 16 G/64 G bit Flash memories and beyond.