UNIVERCM: The UNIversal VERsatile Computational Model for Heterogeneous System Integration

• Published in: IEEE transactions on computers Vol. 62; no. 2; pp. 225 - 241
• Main Authors: Di Guglielmo, L., Fummi, F., Pravadelli, G., Stefanni, F., Vinco, S.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.02.2013; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Automata; Computation; Computational modeling; Computer simulation; Delay; Design; Design engineering; electronic design automation; Formal specifications; Heterogeneity; Mathematical models; modeling; Multiprocessing; multiprocessor; Semantics; simulation; Studies; Syntactics; Systems integration; Valves; Wires
• ISSN: 0018-9340; 1557-9956
• DOI: 10.1109/TC.2012.156

Designers are more and more forced to define innovative models and methodologies for managing integration of heterogeneous components and heterogeneous Chip Multiprocessors (CMPs) in modern embedded systems. In this context, component-based design seems the more promising approach, but it suffers from the lack of a widely adopted Model of Computation (MoC) able to capture component heterogeneity. This paper proposes univerCM, a new model of computation based on the Heterogeneous Intermediate Format (HIF) with the aim of supporting bottom-up design and system integration from a set of heterogeneous components. HW and SW components can be described by means of different languages and according to different MoCs, toward a uniform intermediate description based on a rigorous semantics. A mapping from univerCM to SystemC is proposed then to obtain a homogeneous description intended for fast simulation, that can be also used as starting point for CMP design flows. Experimental results show the effectiveness of univerCM in managing system heterogeneity.