Mitigating Asymmetric Nonlinear Weight Update Effects in Hardware Neural Network Based on Analog Resistive Synapse

• Published in: IEEE journal on emerging and selected topics in circuits and systems Vol. 8; no. 1; pp. 116 - 124
• Main Authors: Chang, Chih-Cheng, Chen, Pin-Chun, Chou, Teyuh, Wang, I-Ting, Hudec, Boris, Chang, Che-Chia, Tsai, Chia-Ming, Chang, Tian-Sheuan, Hou, Tuo-Hung
• Format: Journal Article
• Language: English
• Published: Piscataway IEEE 01.03.2018; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Asymmetry; Biological neural networks; Circuits and systems; Handwriting; Hardware; Machine learning; multilayer perceptron; Multilayer perceptrons; Neural networks; Neuromorphic computing; Neurons; Nonlinearity; RRAM; synapse; Synapses; Training; Upgrading
• ISSN: 2156-3357; 2156-3365
• DOI: 10.1109/JETCAS.2017.2771529

Asymmetric nonlinear weight update is considered as one of the major obstacles for realizing hardware neural networks based on analog resistive synapses, because it significantly compromises the online training capability. This paper provides new solutions to this critical issue through co-optimization with the hardware-applicable deep-learning algorithms. New insights on engineering activation functions and a threshold weight update scheme effectively suppress the undesirable training noise induced by inaccurate weight update. We successfully trained a two-layer perceptron network online and improved the classification accuracy of MNIST handwritten digit data set to 87.8%/94.8% by using 6-/8-b analog synapses, respectively, with extremely high asymmetric nonlinearity.