Thermal strain relaxation of GaAs overgrown on nanovoid based Ge/Si substrate

•Dislocations-mediated porosification of germanium on silicon.•Growth on porous Ge and formation of a two-dimensional nanovoids layer.•Gallium arsenide thermal strain relaxation on germanium nanovoided virtual substrate.•Improvement of the crystal and optical qualities of the GaAs grown on NVS. The...

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Bibliographic Details
Published inJournal of crystal growth Vol. 624; p. 127433
Main Authors Henriques, Jonathan, Ilahi, Bouraoui, Heintz, Alexandre, Morris, Denis, Arès, Richard, Boucherif, Abderraouf
Format Journal Article
LanguageEnglish
Published Elsevier B.V 15.12.2023
Elsevier
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Summary:•Dislocations-mediated porosification of germanium on silicon.•Growth on porous Ge and formation of a two-dimensional nanovoids layer.•Gallium arsenide thermal strain relaxation on germanium nanovoided virtual substrate.•Improvement of the crystal and optical qualities of the GaAs grown on NVS. The integration of high quality III-V materials-based devices on the Si platform is considered as an enabling path towards achieving the long-standing goal of creating low-cost/high-performance devices. However, the heteroepitaxy of III-V compounds on a Si substrate generates high stress due to the difference in thermal expansion coefficient leading notably to crack generation. Here, we report on the reduction of the thermal strain of GaAs and Ge deposited on a Si substrate. The method is based on the formation of buried high density nanovoids by electrochemical etching of Ge/Si virtual substrate followed by direct epitaxial growth of Ge and GaAs. The thermal strain has been investigated for GaAs epilayer by High-Resolution X-Ray Diffraction and Raman spectroscopy showing a 30% decrease in strain. The strain reduction relies on the nanovoids-mediated thermal strain accommodation. Furthermore, photoluminescence measurements showed a 10-fold increase of the intensity, resulting in an improved optical and crystalline quality, making this virtual substrate promising for III-V based devices on Silicon.
ISSN:0022-0248
1873-5002
DOI:10.1016/j.jcrysgro.2023.127433