A Highly Digital MDLL-Based Clock Multiplier That Leverages a Self-Scrambling Time-to-Digital Converter to Achieve Subpicosecond Jitter Performance

• Published in: IEEE journal of solid-state circuits Vol. 43; no. 4; pp. 855 - 863
• Main Authors: Helal, B.M., Straayer, M.Z., Gu-Yeon Wei, Perrott, M.H.
• Format: Journal Article Conference Proceeding
• Language: English
• Published: New York, NY IEEE 01.04.2008; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Circuit optimization; Circuit properties; Circuits; Circuits of signal characteristics conditioning (including delay circuits); Clocks; Converters; Correlated double sampling; correlation; Delay; Design. Technologies. Operation analysis. Testing; deterministic jitter; Digital; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; first-order noise shaping; gated ring oscillator (GRO); Integrated circuit noise; Integrated circuits; Jitter; Multi-stage noise shaping; multiplying delay-locked loop (MDLL); Noise; Oscillators; Oscillators, resonators, synthetizers; Phase locked loops; Prototypes; reference spur; Ring oscillators; Sampling techniques; scrambling; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Shape; Signal convertors; time-to-digital converter (TDC); Tuning; Performance evaluation; Prototype; scrambling; first-order noise shaping; Jitter; gated ring oscillator (GRO); Digital converter; Ring oscillator; Frequency converter; Time to digital conversion; Active filter; deterministic jitter; Time converter; multiplying delay-locked loop (MDLL); Sampling; Root mean square value; Deterministic approach; reference spur; Field programmable gate array; Noise shaping; DA converter; Tuning circuit; Mismatching; RC filter; Correlated double sampling; Phase locked loop; Quantization noise; Continuous time filters; time-to-digital converter (TDC); Frequency multiplier; correlation; First order; Integrated circuit; Delay lock loops
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2008.917372

This paper presents a mostly digital multiplying delay-locked loop (MDLL) architecture that leverages a new time-to-digital converter (TDC) and a correlated double-sampling technique to achieve subpicosecond jitter performance. The key benefit of the proposed structure is that it provides a highly digital technique to reduce deterministic jitter in the MDLL output with low sensitivity to mismatch and offset in the associated tuning circuits. The TDC structure, which is based on a gated ring oscillator (GRO), is expected to benefit other PLL/DLL applications as well due to the fact that it scrambles and first-order noise shapes its associated quantization noise. Measured results are presented of a custom MDLL prototype that multiplies a 50 MHz reference frequency to 1.6 GHz with 928 fs rms jitter performance. The prototype consists of two 0.13 mum integrated circuits, which have a combined active area of 0.06 mm 2 and a combined core power of 5.1 mW, in addition to an FPGA board, a discrete DAC, and a simple RC filter.