3-D Multilayer Copper Interconnects for High-Performance Monolithic Devices and Passives

This paper presents a new and efficient low-cost multilayer 3-D copper interconnect process for monolithic devices and passives. It relies on the BPN and SU-8 photoresists, associated with an optimized electroplating process to form multilevel 3-D interconnects in a single metallization step. The SU...

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Bibliographic Details
Published inIEEE transactions on components, packaging, and manufacturing technology (2011) Vol. 3; no. 6; pp. 935 - 942
Main Authors Ghannam, A., Bourrier, D., Ourak, L., Viallon, C., Parra, T.
Format Journal Article
LanguageEnglish
Published IEEE 01.06.2013
Subjects
Above-IC
BPN
copper
electroplating
high-Q
inductor
interconnect
monolithic microwave integrated circuit (MMIC)
photoresist
process
SU-8
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Summary:This paper presents a new and efficient low-cost multilayer 3-D copper interconnect process for monolithic devices and passives. It relies on the BPN and SU-8 photoresists, associated with an optimized electroplating process to form multilevel 3-D interconnects in a single metallization step. The SU-8 is used as a permanent thick dielectric layer that is patterned underneath specific locations to create the desired 3-D interconnect shape. A 3-D seed layer is deposited above the SU-8 and the substrate to ensure 3-D electroplating current flow. The BPN is used as a thick mold for copper electroplating with an aspect ratio as high as 16:1. An optimized 3-D copper electroplating process is later used to grow 3-D interconnects, ensuring transition between all metallic layers. Finally, high-Q (55 at 5 GHz) power inductors are designed and integrated above a 50 W RF power laterally diffused metal oxide semiconductor device using this process.
ISSN:2156-3950
2156-3985
DOI:10.1109/TCPMT.2013.2258073