PLR: A Software Approach to Transient Fault Tolerance for Multicore Architectures

• Published in: IEEE transactions on dependable and secure computing Vol. 6; no. 2; pp. 135 - 148
• Main Authors: Shye, A., Blomstedt, J., Moseley, T., Reddi, V.J., Connors, D.A.
• Format: Journal Article
• Language: English
• Published: Washington IEEE 01.04.2009; IEEE Computer Society
• Subjects: Application software; Computer architecture; Computer engineering; Computer programs; Computer science; Design; Determinism; Digital Object Identifier; Fault tolerance; Faults; Hardware; Microprocessors; Multicore processing; Operating systems; Performance evaluation; process-level redundancy; Prototypes; Redundancy; Reliability; soft errors; Software; Software prototyping; Software reliability; Studies; Systems analysis; transient faults; Transistors; Trends; Fault-tolerance; Redundant design
• ISSN: 1545-5971; 1941-0018
• DOI: 10.1109/TDSC.2008.62

Transient faults are emerging as a critical concern in the reliability of general-purpose microprocessors. As architectural trends point toward multicore designs, there is substantial interest in adapting such parallel hardware resources for transient fault tolerance. This paper presents process-level redundancy (PLR), a software technique for transient fault tolerance, which leverages multiple cores for low overhead. PLR creates a set of redundant processes per application process and systematically compares the processes to guarantee correct execution. Redundancy at the process level allows the operating system to freely schedule the processes across all available hardware resources. PLR uses a software-centric approach to transient fault tolerance, which shifts the focus from ensuring correct hardware execution to ensuring correct software execution. As a result, many benign faults that do not propagate to affect program correctness can be safely ignored. A real prototype is presented that is designed to be transparent to the application and can run on general-purpose single-threaded programs without modifications to the program, operating system, or underlying hardware. The system is evaluated for fault coverage and performance on a four-way SMP machine and provides improved performance over existing software transient fault tolerance techniques with a 16.9 percent overhead for fault detection on a set of optimized SPEC2000 binaries.