Area-Efficient Bidirectional Shift-Register Using Bidirectional Pulsed-Latches

• Published in: IEEE transactions on circuits and systems. II, Express briefs Vol. 66; no. 8; pp. 1386 - 1390
• Main Authors: Woo, Ki-Chan, Kang, Hyeong-Ju, Yang, Byung-Do
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.08.2019; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Area-efficient; bidirectional shift-register; Clocks; CMOS; CMOS process; Delays; flip-flop; Flip-flops; Latches; Master-slave; Multiplexers; Multiplexing; Power consumption; Power demand; pulsed clock; pulsed-latch
• ISSN: 1549-7747; 1558-3791
• DOI: 10.1109/TCSII.2018.2882810

This brief proposes an area-efficient bidirectional shift-register using bidirectional pulsed-latches. The proposed bidirectional shift-register reduces the area and power consumption by replacing master-slave flip-flops and 2-to-1 multiplexers with the proposed bidirectional pulsed-latches and non-overlap delayed pulsed clock signals, and by using sub shift-registers and extra temporary storage latches. A 256-bit bidirectional shift-register was fabricated using a 65 nm CMOS process. Its area was 1943 μm2 and its power consumption is 200 μW at a 100 MHz clock frequency with VDD = 1.2 V. It reduces area by 39.2% and power consumption by 19.4% compared to the conventional bidirectional shift-register.