Test consideration for nanometer-scale CMOS circuits

The exponential increase in leakage, the device parameter variations, and the aggressive power management techniques will severely impact IC testing methods. Test technology faces new challenges as faults with increasingly complex behavior become predominant. Design approaches aimed at fixing some o...

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Bibliographic Details
Published inIEEE design & test of computers Vol. 23; no. 2; pp. 128 - 136
Main Authors Kaushik Roy, Mak, T.M., Cheng, K.-T.
Format Journal Article
LanguageEnglish
Published IEEE Computer Society 01.03.2006
Subjects
Circuit faults
Circuit testing
Circuits
CMOS
CMOS technology
deep-submicron test
Delay
delay test
Faults
Frequency
Leakage
Management
nanometer technologies
Silicon
statistical timing
Temperature dependence
Thermal management
Threshold voltage
Time measurements
Timing
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Summary:The exponential increase in leakage, the device parameter variations, and the aggressive power management techniques will severely impact IC testing methods. Test technology faces new challenges as faults with increasingly complex behavior become predominant. Design approaches aimed at fixing some of the undesirable effects of nanometric technologies could jeopardize current test approaches. In this article, we explore test considerations for scaled CMOS circuits in the nanometer regime and describe possible solutions to many of these challenges, including statistical timing and delay test, I/sub DDQ/ test under exponentially increasing leakage, and power or thermal management architectures.
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ISSN:0740-7475
1558-1918
DOI:10.1109/MDT.2006.52