8.2‐GHz band radar RFICs for an 8 × 8 phased‐array FMCW receiver developed with 65‐nm CMOS technology

• Published in: ETRI journal Vol. 42; no. 6; pp. 943 - 950
• Main Authors: Han, Seon‐Ho, Koo, Bon‐Tae
• Format: Journal Article
• Language: English
• Published: Electronics and Telecommunications Research Institute (ETRI) 01.12.2020; 한국전자통신연구원
• Subjects: FMCW; phase shifter; phased array; radar; receiver; 전자/정보통신공학
• ISSN: 1225-6463; 2233-7326
• DOI: 10.4218/etrij.2020-0046

We propose 8.2‐GHz band radar RFICs for an 8 × 8 phased‐array frequency‐modulated continuous‐wave receiver developed using 65‐nm CMOS technology. This receiver panel is constructed using a multichip solution comprising fabricated 2 × 2 low‐noise amplifier phase‐shifter (LNA‐PS) chips and a 4ch RX front‐end chip. The LNA‐PS chip has a novel phase‐shifter circuit for low‐voltage operation, novel active single‐to‐differential/differential‐to‐single circuits, and a current‐mode combiner to utilize a small area. The LNA‐PS chip shows a power gain range of 5 dB to 20 dB per channel with gain control and a single‐channel NF of 6.4 dB at maximum gain. The measured result of the chip shows 6‐bit phase states with a 0.35˚ RMS phase error. The input P1 dB of the chip is approximately –27.5 dBm at high gain and is enough to cover the highest input power from the TX‐to‐RX leakage in the radar system. The gain range of the 4ch RX front‐end chip is 9 dB to 30 dB per channel. The LNA‐PS chip consumes 82 mA, and the 4ch RX front‐end chip consumes 97 mA from a 1.2 V supply voltage. The chip sizes of the 2 × 2 LNA‐PS and the 4ch RX front end are 2.39 mm × 1.3 mm and 2.42 mm × 1.62 mm, respectively.