An extendable single‐input reduced‐switch 11‐level switched‐capacitor inverter with quintuple boosting factor

• Published in: IET generation, transmission & distribution Vol. 17; no. 3; pp. 621 - 631
• Main Authors: Deliri, Saeid, Varesi, Kazem, Padmanaban, Sanjeevikumar
• Format: Journal Article
• Language: English
• Published: Wiley 01.02.2023
• ISSN: 1751-8687; 1751-8695
• DOI: 10.1049/gtd2.12416

This paper proposes a novel single‐phase switched‐capacitor‐based inverter configuration that in its basic form can generate an 11‐level staircase output voltage waveform with sinusoidal output current for Resistive‐Inductive (R‐L) loads. The increased levels, quintuple voltage‐boosting factor, and natural voltage‐balancing of capacitors are considered the main features of the proposed basic configuration. The proposed topology requires fewer components (resources, switches, driver circuits, and capacitors) than recently presented similar structures to acquire the same voltage gain and output steps. The proposed basic configuration can be extended in two ways: increasing levels and/or boosting factors with minimal devices. The employment of two half‐bridges (rather than an H‐bridge) for generating bipolar waveform has limited the number of switches tolerating the maximum output voltage to 2 (instead of 4), which results in reduced total blocking voltage (TBV) and accordingly reduced cost and losses. A comprehensive comparative analysis has been done and presented to verify the supremacy of the suggested structure. The experimental results of the laboratory‐scaled prototype of the proposed basic topology have been provided, which approve its correct performance.