Symmetrical ESD trigger and pull-up using BIMOS transistor in advanced CMOS technology

The purpose of this paper is to present a new trigger design solution to address a double challenge. The first challenge is to trigger a dual back to back SCR during an ESD event with symmetrical response. And the second one is to obtain a pull-up function for the normal mode of the protection. Thes...

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Bibliographic Details
Published inMicroelectronics and reliability Vol. 52; no. 9-10; pp. 1998 - 2004
Main Authors Galy, Ph, Bourgeat, J., Jimenez, J., Guitard, N., Dray, A., Troussier, G., Jacquier, B., Marin-Cudraz, D.
Format Journal Article Conference Proceeding
LanguageEnglish
Published Kidlington Elsevier Ltd 01.09.2012
Elsevier
Subjects
Applied sciences
Design. Technologies. Operation analysis. Testing
Electronic equipment and fabrication. Passive components, printed wiring boards, connectics
Electronics
Exact sciences and technology
Integrated circuits
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Transistors
Trigger
Transmission line
Circuit design
Complementary MOS technology
Electrostatic discharge
Transistor
Silicon
Advanced technology
Computer aided design
Pulse measurement
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Summary:The purpose of this paper is to present a new trigger design solution to address a double challenge. The first challenge is to trigger a dual back to back SCR during an ESD event with symmetrical response. And the second one is to obtain a pull-up function for the normal mode of the protection. These targets are reached thanks to BIMOS transistor approach compatible with advanced CMOS technology. Moreover, the silicon area constraint is addressed. The study through 3D TCAD simulation is performed on 40nm and 32nm and includes Transmission Line Pulse (TLP) measurements of a demonstrator circuit.
ISSN:0026-2714
1872-941X
DOI:10.1016/j.microrel.2012.06.117