Device-level early floorplanning algorithms for RF circuits

High-frequency circuits are notoriously difficult to lay out because of the tight coupling between device-level placement and wiring. Given that successful electrical performance requires careful control of the lowest-level geometric features-wire bends, precise length, planarity, etc., we suggest a...

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Bibliographic Details
Published inIEEE transactions on computer-aided design of integrated circuits and systems Vol. 18; no. 4; pp. 375 - 388
Main Authors Aktuna, M., Rutenbar, R.A., carley, L.R.
Format Journal Article Conference Proceeding
LanguageEnglish
Published New York, NY IEEE 01.04.1999
Institute of Electrical and Electronics Engineers
Subjects
Algorithms
Applied sciences
Bends
Central Processing Unit
Circuits
Constraint optimization
Coupling circuits
Design automation
Design. Technologies. Operation analysis. Testing
Devices
Electric wire
Electronics
Exact sciences and technology
Floorplans
Genetic algorithms
Integrated circuit layout
Integrated circuits
Placement
Radio frequency
Routing
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Wire
Wiring
Experimental result
Prototype
Genetic algorithm
Integrated circuit
Routing
Performance analysis
High frequency
Computer aided design
Optimization
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Summary:High-frequency circuits are notoriously difficult to lay out because of the tight coupling between device-level placement and wiring. Given that successful electrical performance requires careful control of the lowest-level geometric features-wire bends, precise length, planarity, etc., we suggest a new layout strategy for these circuits: early floorplanning at the device level. This paper develops a floorplanner for radio-frequency circuits based on a genetic algorithm (GA) that supports fully simultaneous placement and routing. The GA evolves slicing-style floorplans comprising devices and planned areas for wire meanders. Each floorplan candidate is fully routed with a gridless, detailed maze-router which can dynamically resize the floorplan as necessary. Experimental results demonstrate the ability of this approach to successfully optimize for wire planarity, realize multiple constraints on net lengths or phases, and achieve reasonable area in modest CPU times.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
ISSN:0278-0070
1937-4151
DOI:10.1109/43.752922