Analysis of Cu/low- k bond pad delamination by using a novel failure index

• Published in: Microelectronics and reliability Vol. 47; no. 2; pp. 179 - 186
• Main Authors: van Gils, M.A.J., van der Sluis, O., Zhang, G.Q., Janssen, J.H.J., Voncken, R.M.J.
• Format: Journal Article Conference Proceeding
• Language: English
• Published: Oxford Elsevier Ltd 01.02.2007; Elsevier
• Subjects: Applied sciences; Design. Technologies. Operation analysis. Testing; Electronics; Exact sciences and technology; Integrated circuits; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; State of the art; Cracking; Numerical method; Adhesion; Failures; Case study; Finite element method; Integrated circuit bonding; Solder bump; Wire bonding; Interconnection; Complementary MOS technology; Electronic packaging; Integrated circuit; Reliability; Delamination; Low k dielectric; Comparative study; Crack
• ISSN: 0026-2714; 1872-941X
• DOI: 10.1016/j.microrel.2006.09.003

For the development of state-of-the-art Cu/low- k CMOS technologies, the integration and introduction of new low- k materials is one of the major bottlenecks owing to the bad thermal and mechanical integrity of these materials and the inherited weak interfacial adhesion. Especially the forces resulting from packaging related processes such as dicing, wire bonding, bumping and molding are critical and can easily result in cracking, delamination and chipping of the IC back-end structure if no appropriate measures are taken. This paper presents a methodology for optimizing the thermo-mechanical reliability of bond pads by using a 3D multi-scale finite element approach. An important characteristic of this methodology is the use of a novel energy-based failure index, which allows a fast qualitative comparison of different back-end structures. The usability of the methodology will be illustrated by a case study in which several bond pad structures are analysed.