A CMOS Dual-Mode Brain-Computer Interface Chipset With 2-mV Precision Time-Based Charge Balancing and Stimulation-Side Artifact Suppression

• Published in: IEEE journal of solid-state circuits Vol. 57; no. 6; pp. 1824 - 1840
• Main Authors: Pu, Haoran, Malekzadeh-Arasteh, Omid, Danesh, Ahmad Reza, Nenadic, Zoran, Do, An H., Heydari, Payam
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.06.2022; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Analog to digital converters; Balancing; Bi-directional brain–computer interface (BD-BCI); Bidirectional control; Brain; Brain stimulation; Chips (electronics); CMOS; Data acquisition; dual-mode data acquisition (DAQ); Electrodes; Feature extraction; Monitoring; multipolar; Recording; Stimulation; stimulation-side artifact cancellation; stimulator; Stimulators; time-based charge balancing (TBCB); ultralow power (ULP); Voltage
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2021.3108578

This article presents a multipolar neural stimulation and mixed-signal neural data acquisition (DAQ) chipset for fully implantable bi-directional brain-computer interfaces (BD-BCIs). The stimulation system employs four 40 V compliant current-stimulators, each capable of sourcing/sinking a maximum 12.75 mA stimulation current, connected to 16 output channels through a high-voltage (HV) switch fabric. A novel time-based charge balancing (TBCB) technique is introduced to reduce the residual voltage on the electrode-electrolyte interface during the inter-pulse time interval, achieving 2 mV charge balancing precision. Additionally, an analytical study of the charge balancing accuracy for the proposed technique is provided. The recording system incorporates a dual-mode DAQ architecture that consists of a 32-element front-end array and a mixed-signal back-end including analog-to-digital converters (ADCs) for both training (i.e., full-band) and decoding (i.e., baseband) operations. Leveraging the flexibility of the multipolar operation, stimulation-side contour shaping (SSCS) artifact cancellation is adopted to significantly suppress stimulation artifacts by up to 45 dB. SSCS method prevents the recording front-ends from saturation and greatly relaxes the dynamic range requirement of the recording system, enabling a truly bi-directional operation. The prototype chipset is fabricated in an HV 180-nm CMOS process and demonstrates a significant performance improvement compared to the prior art.