Associative memory architecture for word-parallel smallest Euclidean distance search using distance mapping into clock-number domain

• Published in: Japanese Journal of Applied Physics Vol. 53; no. 4S; pp. 4 - 1-04EE16-7
• Main Authors: Akazawa, Toshinobu, Sasaki, Seiryu, Mattausch, Hans Jürgen
• Format: Journal Article
• Language: English
• Published: The Japan Society of Applied Physics 01.04.2014
• Subjects: Architecture; Associative memory; Chip formation; CMOS; Mapping; Mathematical analysis; Optimization; Searching; Vectors (mathematics)
• ISSN: 0021-4922; 1347-4065
• DOI: 10.7567/JJAP.53.04EE16

A scalable word-parallel associative memory for smallest Euclidean distance (ED) search is presented. Due to the applied concept of distance to clock-number mapping, the reported architecture is digital in nature and scalable to advanced technology. Furthermore, the reference data of feature vectors can be scaled in principle to any vector dimension and number. Handling of the numerical complexity of the ED without large consumption of Silicon area is achieved by an area-efficient circuit, which uses the same adder for absolute-difference calculation of vector components and subsequent square calculation by sequential addition of partial products. Additionally, a clock-number minimization algorithm is proposed to significantly reduce the clock-number needed for the search when the smallest ED is a large value. The concept of the proposed architecture has been experimentally verified by measurement results from real chips fabricated in a 180 nm CMOS technology, in which the architecture is configured for parallel smallest ED search among 32 reference vectors with each vector having 16 8-bit elements. For the application example of codebook-based data compression, the fabricated test chip achieved 1.19 µs average search time, 5.77 µs worst-case search time and low power consumption of 8.75 mW at the maximum clock frequency of 47 MHz and nominal power supply voltage Vdd = 1.8 V. At reduced power supply voltage Vdd = 1.2 V, a smaller power consumption of 2.80 mW at an also smaller maximum clock frequency of 24 MHz is measured. In comparison to previous analog-digital architecture, a reduction of the normalized power-delay product per matching operation by about a factor 1.6 at Vdd = 1.8 V (about factor 2.5 at Vdd = 1.2 V) is obtained with best-case data for the analog-digital architecture and average-case data for the proposed fully-digital architecture.