Effects of multithreading on cache performance

As the performance gap between processor and memory grows, memory latency becomes a major bottleneck in achieving high processor utilization. Multithreading has emerged as one of the most promising and exciting techniques used to tolerate memory latency by exploiting thread-level parallelism. The qu...

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Bibliographic Details
Published inIEEE transactions on computers Vol. 48; no. 2; pp. 176 - 184
Main Authors Kwak, H., Lee, B., Hurson, A.R., Suk-Han Yoon, Woo-Jong Hahn
Format Journal Article
LanguageEnglish
Published IEEE 01.02.1999
Subjects
Computer simulation
Computer Society
Costs
Delay
Hierarchies
Management
Memory management
Microprocessors
Multithreading
Parallel processing
Processor scheduling
Programming
Scheduling
Stress
Switches
Switching
Utilization
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Summary:As the performance gap between processor and memory grows, memory latency becomes a major bottleneck in achieving high processor utilization. Multithreading has emerged as one of the most promising and exciting techniques used to tolerate memory latency by exploiting thread-level parallelism. The question, however, remains as to how effective multithreading is on tolerating memory latency. The performance of multithreading is not only affected by the overlapping of memory latency with useful computation, but also strongly depends on the cache behavior and the overhead of multithreading (e.g., thread management and context-switch costs). In particular, multithreading affects the behavior of caches, and, thus, the overall performance in a nontrivial fashion. To study these issues, this paper presents the Multithreaded Virtual Processor (MVP) model. MVP integrates the multithreaded programming paradigm and a modern superscalar processor with support for fast context switching and thread scheduling. Our studies with MVP show that, in general, the performance improvements are obtained not only by tolerating memory latency but also lower cache miss rates due to exploitation of data locality. However, multithreading creates an additional stress on the memory hierarchy caused by the interference among threads. Also, the dynamic behavior of multithreaded execution hinders the instruction locality that results in a high number of misses in the L1 instruction cache.
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ISSN:0018-9340
1557-9956
DOI:10.1109/12.752659