Effect of Ge Metal--Insulator--Semiconductor Interfacial Layers on Interface Trap Density near the Conduction Band Edge

• Published in: Japanese Journal of Applied Physics Vol. 49; no. 4; pp. 04DA09 - 04DA09-6
• Main Authors: Taoka, Noriyuki, Mizubayashi, Wataru, Morita, Yukinori, Migita, Shinji, Ota, Hiroyuki, Takagi, Shinichi
• Format: Journal Article
• Language: English
• Published: The Japan Society of Applied Physics 01.04.2010
• ISSN: 0021-4922; 1347-4065
• DOI: 10.1143/JJAP.49.04DA09

The interface structures and electrical interface properties near the conduction band edge (CBE) of Ge metal--insulator--semiconductor (MIS) capacitors with Si or GeO 2 interfacial layers (ILs) were systematically investigated using physical analysis and the Gray--Brown (GB) method. The accuracy of the values of interface trap density ($D_{\text{it}}$) obtained by the GB method was confirmed by comparing these with the values obtained by the conductance method. The GB method revealed that Ge MIS capacitors with a Si IL have a large number of interface traps near the CBE, and that the dislocations introduced at a Si IL/Ge interface have an insignificant effect on $D_{\text{it}}$ near CBE. On the other hand, the $D_{\text{it}}$ of the GeO 2 IL capacitors was lower by almost one order of magnitude than that of the Si IL capacitors. In addition, the $D_{\text{it}}$ of the GeO 2 IL/Ge interface was also reduced by high-temperature oxidation during post metallization annealing. These results indicate that ILs have a strong influence on $D_{\text{it}}$ near the CBE, and that the GeO 2 IL and high-temperature oxidation are quite effective in reducing $D_{\text{it}}$ near the CBE.