XNOR-Bitcount Operation Exploiting Computing-In-Memory With STT-MRAMs

This brief presents an energy-efficient and highperformance XNOR-bitcount architecture exploiting the benefits of computing-in-memory (CiM) and unique properties of spintransfer torque magnetic RAM (STT-MRAM) based on doublebarrier magnetic tunnel junctions (DMTJs). Our work proposes hardware and al...

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Bibliographic Details
Published inIEEE transactions on circuits and systems. II, Express briefs Vol. 70; no. 3; p. 1
Main Authors Musello, Ariana, Garzon, Esteban, Lanuzza, Marco, Procel, Luis Miguel, Taco, Ramiro
Format Journal Article
LanguageEnglish
Published New York IEEE 01.03.2023
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects
Algorithms
bit-quad
BNN
CNN
Computation
Computing-in-memory
DMTJ
Energy consumption
Hardware
MAC
Magnetic properties
Magnetic tunneling
Optimization
Random access memory
Shape
spin-transfer torque
STT-MRAM
Switches
Torque
Transistors
Tunnel junctions
XNOR-bitcount
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Summary:This brief presents an energy-efficient and highperformance XNOR-bitcount architecture exploiting the benefits of computing-in-memory (CiM) and unique properties of spintransfer torque magnetic RAM (STT-MRAM) based on doublebarrier magnetic tunnel junctions (DMTJs). Our work proposes hardware and algorithmic optimizations, benchmarked against a state-of-the-art CiM-based XNOR-bitcount design. Simulation results show that our hardware optimization reduces the storage requirement (-50%) for each XNOR-bitcount operation. The proposed algorithmic optimization improves execution time and energy consumption by about 30% (78%) and 26% (85%), respectively, for single (5 sequential) 9-bit XNOR-bitcount operations. As a case study, our solution is demonstrated for shape analysis using bit-quads.
ISSN:1549-7747
1558-3791
DOI:10.1109/TCSII.2023.3241163