(Invited) Very Low Temperature Epitaxy of Group-IV Semiconductors for Use in FinFET, Stacked Nanowires and Monolithic 3D Integration

As CMOS scaling proceeds with sub-10 nm nodes, new architectures and materials are implemented to continue increasing performances at constant footprint. Strained and stacked channels and 3D-integrated devices have for instance been introduced for this purpose. A common requirement for these new tec...

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Published inECS transactions Vol. 86; no. 7; pp. 163 - 175
Main Authors Porret, Clement, Hikavyy, Andriy Yakovitch, Gomez Granados, Juan Fernando, Baudot, Sylvain, Vohra, Anurag, Kunert, Bernardette, Douhard, Bastien, Bogdanowicz, Janusz, Schaekers, Marc, Kohen, David, Margetis, Joe, Tolle, John, Lima, Lucas, Sammak, Amir, Scappucci, Giordano, Rosseel, Erik, Langer, Robert, Loo, Roger
Format Journal Article
LanguageEnglish
Published The Electrochemical Society, Inc 20.07.2018
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Summary:As CMOS scaling proceeds with sub-10 nm nodes, new architectures and materials are implemented to continue increasing performances at constant footprint. Strained and stacked channels and 3D-integrated devices have for instance been introduced for this purpose. A common requirement for these new technologies is a strict limitation in thermal budgets to preserve the integrity of devices already present on the chips. We present our latest developments on low-temperature epitaxial growth processes, ranging from channel to source/drain applications for a variety of devices and describe options to address the upcoming challenges.
ISSN:1938-5862
1938-6737
1938-6737
1938-5862
DOI:10.1149/08607.0163ecst