Electrical stabilities of half-Corbino thin-film transistors with different gate geometries

• Published in: Journal of Information Display Vol. 13; no. 1; pp. 51 - 54
• Main Authors: Jung, Hyunseung, Choi, Keun-Yeong, Lee, Hojin
• Format: Journal Article
• Language: English
• Published: Taylor & Francis 01.03.2012; 한국정보디스플레이학회
• Subjects: bias-temperature stress; current-temperature stress; gate geometry; half-Corbino; thin-film transistor; 전기공학
• ISSN: 1598-0316; 2158-1606
• DOI: 10.1080/15980316.2011.652197

In this study, the bias-temperature stress and current-temperature stress induced by the electrical stabilities of half-Corbino hydrogenated-amorphous-silicon (a-Si:H) thin-film transistors (TFTs) with different gate electrode geometries fabricated on the same substrate were examined. The influence of the gate pattern on the threshold voltage shift of the half-Corbino a-Si:H TFTs is discussed in this paper. The results indicate that the half-Corbino a-Si:H TFT with a patterned gate electrode has enhanced power efficiency and improved aperture ratio when compared with the half-Corbino a-Si:H TFT with an unpatterned gate electrode and the same source/drain electrode geometry.