An SFS Berger check prediction ALU and its application to self-checking processor designs

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 11; no. 4; pp. 525 - 540
• Main Authors: Lo, J.-C., Thanawastien, S., Rao, T.R.N., Nicolaidis, M.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.04.1992; Institute of Electrical and Electronics Engineers
• Subjects: Applied sciences; Built-in self-test; Business continuity; Circuit faults; Computer errors; Costs; Electronics; Engineering Sciences; Error correction; Exact sciences and technology; Hardware; Integrated circuits; Integrated circuits by function (including memories and processors); Micro and nanotechnologies; Microelectronics; Process design; Registers; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Very large scale integration; VLSI-ALU; BIST; error-models; Berger-check-prediction; self-checking-processor-designs; strongly-fault-secure; self-testing; Berger-code; fault-models
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/43.125100

A strongly fault secure (SFS) ALU design based on the Berger check prediction (BCP) technique is presented. The fault and error models of a large class of VLSI ALU designs are discussed. The proposed design is proved to be fault-secure and self-testing with respect to any single fault in the ALU part. The proposed BCP ALU is proved to be SFS with any design of BCP circuit. Consequently, a self-checking processor whose data path is encoded entirely in a Berger code can be achieved. An efficient self-checking processor can then be designed.< >