Design and Implementation of an Ultralow-Energy FFT ASIC for Processing ECG in Cardiac Pacemakers

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 27; no. 4; pp. 983 - 987
• Main Authors: Noor, Safwat Mostafa, John, Eugene, Panday, Manoj
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.04.2019; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Application specific integrated circuits; Batteries; Biomedical materials; Block floating point (BFP); cardiac pacemaker; Circuit design; Clocks; Computer simulation; electrocardiogram (ECG); Electrocardiography; Embedded systems; Energy consumption; fast Fourier transform (FFT); Fast Fourier transformations; Fourier transforms; hash; Integrated circuits; lookup table (LUT); Lookup tables; low-power application specific integrated circuit (ASIC); Pacemakers; Power consumption; Power demand; Signal processing; Signal processing algorithms; Spectrum analysis; Surgical implants; Very large scale integration
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2018.2883642

In embedded biomedical applications, spectrum analysis algorithms such as fast Fourier transform (FFT) are crucial for pattern detection and have been the focus of continued research. In deeply embedded systems such as cardiac pacemakers, FFT-based signal processing is typically computed by application-specific integrated circuit (ASIC) to achieve low-power operation. This brief proposes a data-driven design approach for an FFT ASIC solution, which exploits the limited range of data encountered by these embedded systems. The optimizations proposed in this brief use the simple concept of hashing and lookup table to effectively reduce the number of arithmetic operations required to perform the FFT of an electrocardiogram (ECG) signal. By reducing the dynamic power consumption and overall energy footprint of FFT computation, the proposed design aims to achieve longer battery life for a cardiac pacemaker. The design is synthesized using a 90-nm standard cell library, and gate level switching activity is simulated to obtain accurate power consumption results. The proposed optimizations achieved a low energy consumption of 27.72 nJ per FFT, which is 14.22% lower than a standard 128-point radix-2 FFT when tested with actual ECG data collected from PhysioNet.