Efficient Backside Power Delivery for High-Performance Computing Systems

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 30; no. 11; pp. 1748 - 1756
• Main Authors: Lin, Hesheng, van der Plas, Geert, Sun, Xiao, Velenis, Dimitrios, Catthoor, Francky, Lauwereins, Rudy, Beyne, Eric
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.11.2022; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Air-core inductor; backside power delivery network (PDN); buck converter; Buck converters; Business process re-engineering; CAD; Capacitors; Computation; Computer aided design; Density; Design optimization; Efficiency; Electric power; Electricity generation; Energy dissipation; High performance computing; Inductors; Integrated circuits; Interconnections; Resistance; Switches; system integration; system optimization; Voltage; Voltage control; Voltage regulators
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2022.3183904

In this work, we present a thin-profile, efficient power delivery approach, including a voltage regulator with in-package power inductor and backside power delivery network (PDN). To meet 1-<inline-formula> <tex-math notation="LaTeX">\mathrm {W}/{\mathrm {mm}}^{2} </tex-math></inline-formula> power-density target for high-performance computing (HPC) systems, a 25-high-<inline-formula> <tex-math notation="LaTeX">Q </tex-math></inline-formula>-factor (300 MHz), 150-<inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math></inline-formula>-thick, in-molding power inductor is provided for high-efficiency point-of-load (PoL) voltage regulation. Meanwhile, a novel analytical model for backside power delivery is developed for computer-aided-design (CAD) procedure to optimize the system efficiency. For the power flowing from bumps (57-<inline-formula> <tex-math notation="LaTeX">\mu \text{m} V_{\mathrm {DD}} </tex-math></inline-formula>-bump pitch) and backside PDN to active devices, the area resistances contributed by backside PDN and the buried power rail (BPR) are 23% and 77%, respectively, if a 10-<inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math></inline-formula>-horizontal-pitch nano- through-silicon via (<inline-formula> <tex-math notation="LaTeX">n </tex-math></inline-formula>TSV) is available. The resulting impact on power dissipation is within 1% so negligible. A higher ratio (0.5) buck converter with maintained efficiency is combined to better benefit the external interconnect. The overall power delivery efficiency <inline-formula> <tex-math notation="LaTeX">\eta \,\,=83 </tex-math></inline-formula>% can be obtained for 1-<inline-formula> <tex-math notation="LaTeX">\mathrm {W}/{\mathrm {mm}}^{2} </tex-math></inline-formula> power-density target. The power losses contributed by an air-core inductor, power switches, and PDN/BPR/redistribution layer (RDL) are 26%, 66%, and 8%, respectively.