Co-design of SLC/MLC FeFET-based highly error-tolerant low-power CiM and strong lottery ticket hypothesis-based algorithm

• Published in: Japanese Journal of Applied Physics Vol. 63; no. 4; pp. 4 - 16
• Main Authors: Yamauchi, Kenshin, Yamada, Ayumu, Misawa, Naoko, Cho, Seong-Kun, Toprasertpong, Kasidit, Takagi, Shinichi, Matsui, Chihiro, Takeuchi, Ken
• Format: Journal Article
• Language: English
• Published: Tokyo IOP Publishing 01.04.2024; Japanese Journal of Applied Physics
• Subjects: Accuracy; Algorithms; Co-design; Computation-in-Memory; FeFET; Hypotheses; Inference; Mapping; Neural networks; Power consumption; Power management; Strong Lottery Ticket Hypothesis; Weight reduction
• ISSN: 0021-4922; 1347-4065
• DOI: 10.35848/1347-4065/ad2656

Abstract This study co-designs single-level cell (SLC) mask and multilevel cell (MLC) weight twin FeFET devices and a strong lottery ticket hypothesis (SLTH)-based neural network (NN) algorithm to achieve highly error-tolerant low-power Computation-in-Memory (CiM). The SLC mask FeFET masks or transfers the NN weight stored in the MLC weight FeFET, and the masked NN weight reduces the CiM power consumption. The proposed SLC mask FeFETs, which are trained, and MLC weight FeFETs, in which V TH are uniformly randomized, achieve 87% inference accuracy against 10-year data retention and read disturb. The SLC mask FeFETs show 86% inference accuracy even at 2000 endurance cycles. In addition, shared-bottom-select-gate (BSG) SLTH CiM and common-mask SLTH CiM for the NN convolutional layer are proposed to reduce the CiM area by sharing BSG and mask FeFET. Moreover, NN weight mapping schemes for SLTH CiM are proposed. The proposed mapping schemes show a tradeoff between inference accuracy and CiM area. One of the schemes reduces the CiM area by 45% with a 9.1% accuracy loss.