Explicit analysis of channel mismatch effects in time-interleaved ADC systems

• Published in: IEEE transactions on circuits and systems. 1, Fundamental theory and applications Vol. 48; no. 3; pp. 261 - 271
• Main Authors: Kurosawa, N., Kobayashi, H., Maruyama, K., Sugawara, H., Kobayashi, K.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.03.2001; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Bandwidth; Calibration; Circuit noise; Circuit testing; Clocks; Degradation; Instruments; Large scale integration; Sampling methods; Studies; Timing
• ISSN: 1057-7122; 1558-1268
• DOI: 10.1109/81.915383

A time-interleaved A-D converter (ADC) system is an effective way to implement a high-sampling-rate ADC with relatively slow circuits. In the system, several channel ADCs operate at interleaved sampling times as if they were effectively a single ADC operating at a much higher sampling rate. However, mismatches such as offset, gain mismatches among channel ADCs as well as timing skew of the clocks distributed to them degrade S/N of the ADC system as a whole. This paper analyzes the channel mismatch effects in the time-interleaved ADC system. Previous analysis showed the effect for each mismatch individually, however in this paper we derive explicit formulas for the mismatch effects when all of offset, gain and timing mismatches exist together. We have clarified that the gain and timing mismatch effects interact with each other but the offset mismatch effect is independent from them, and this can be seen clearly in frequency domain. We also discuss the bandwidth mismatch effect. The derived formulas can be used for calibration algorithms to compensate for the channel mismatch effects.