Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture With Overlay Via-Switch Crossbars

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 26; no. 12; pp. 2723 - 2736
• Main Authors: Ochi, Hiroyuki, Yamaguchi, Kosei, Fujimoto, Tetsuaki, Hotate, Junshi, Kishimoto, Takashi, Higashi, Toshiki, Imagawa, Takashi, Doi, Ryutaro, Tada, Munehiro, Sugibayashi, Tadahiko, Takahashi, Wataru, Wakabayashi, Kazutoshi, Onodera, Hidetoshi, Mitsuyama, Yukio, Yu, Jaehoon, Hashimoto, Masanori
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.12.2018; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Delays; Field programmable gate array (FPGA); Field programmable gate arrays; Integrated circuit interconnections; Lookup tables; Mapping; non-volatile resistive-change switch; Programming; reconfigurable architecture; Reconfiguration; Switches; Switching circuits; Varistors
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2018.2812914

This paper proposes a highly dense reconfigurable architecture that introduces via-switch device, which is a nonvolatile resistive-change switch and is used in crossbar switches. Via-switch is implemented in back-end-of-line layers only, and hence the front-end-of-line (FEoL) layers under the crossbar can be fully exploited for highly dense logic blocks. The proposed architecture uses the FEoL layers for fine-grained lookup tables and coarse-grained arithmetic/memory units for improving performance and compatibility with various applications. A case study of application mapping shows the proposed architecture can reduce the array area by 21.7%, thanks to the bidirectional interconnection. Thanks to <inline-formula> <tex-math notation="LaTeX">18F^{2} </tex-math></inline-formula> footprint and one order of magnitude lower resistivity of via-switch compared to MOS switch, the crossbar density is improved by up to <inline-formula> <tex-math notation="LaTeX">26\times </tex-math></inline-formula> and the delay and energy in the interconnection are reduced by 90% and 94% at 0.5-V operation.