Modeling, Design, and Analysis of MagnetoElastic NML Circuits

• Published in: IEEE transactions on nanotechnology Vol. 15; no. 6; pp. 977 - 985
• Main Authors: Giri, Davide, Vacca, Marco, Causapruno, Giovanni, Zamboni, Maurizio, Graziano, Mariagrazia
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.11.2016; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Circuit design; Clocks; CMOS; Design analysis; Design engineering; Integrated circuit modeling; Logic; Magnetic circuits; Magnetic domains; Magnetoelastic clock; Magnetoelastic effect; Mathematical models; nano-magnet logic; parallel architectures; Power demand; Switches; Wires
• ISSN: 1536-125X; 1941-0085
• DOI: 10.1109/TNANO.2016.2619377

With the predicted end of CMOS scaling process, researchers started to study several alternative technologies. Among them NanoMagnet Logic (NML) offers advantages complementary to MOS transistors especially for its magnetic nature. Its intrinsic memory capability makes it suitable for zero stand-by power and logic-in-memory applications. NML requires a clock system that, if based on a magnetic field, highly increases the circuit dynamic power consumption. We have recently proposed a solution based on the magnetoelastic effect (ME-NML) [1] and on currently available fabrication processes, which drastically reduces dynamic power consumption. However, many questions still remain unanswered. Which kind of applications are best suited for this technology? How can we effectively design, analyze, and compare ME-NML circuits? Does it really offer advantages over state-of-the-art CMOS transistors? In this paper, we provide answers to all these questions and the results prove that this technology offers indeed extremely good performance. We have designed a Galois field multiplier with a systolic array structure to reduce interconnection overhead. We developed a new RTL model that allows us to easily describe and simulate circuits of any complexity, evaluating at the same time the performance and keeping into account technology constraints. We approach for the first time in the NML scenario the design of ME-NML circuits adopting the standard-cell method used in standard technologies and fulfill the design down to the physical level. The same circuit is designed also with NML technology based on magnetic fields and with a 28 nm low power CMOS bulk technology for comparison. The CMOS circuit is obtained through physical place&route with a commercial tool, providing, therefore, the most accurate comparison ever presented in literature. Power analysis shows that ME-NML circuits have a considerable advantage over both NML and state-of-the-art CMOS bulk technology. As a further by-product results clearly highlight which kind of architectures can better exploit the true potential of NML technology.