A low-jitter PLL clock generator for microprocessors with lock range of 340-612 MHz

• Published in: IEEE journal of solid-state circuits Vol. 34; no. 4; pp. 513 - 519
• Main Author: Boerstler, D.W.
• Format: Journal Article
• Language: English
• Published: IEEE 01.04.1999
• Subjects: Charge pumps; Clock generators; Clocks; Delay; Frequency conversion; Frequency ranges; Jitter; Locks; Microprocessors; Phase locked loops; Power generation; Process design; Rejection; Trees; Voltage-controlled oscillators
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/4.753684

A fully integrated, phase-locked loop (PLL) clock generator/phase aligner for the POWER3 microprocessor has been designed using a 2.5-V, 0.40-/spl mu/m digital CMOS6S process. The PLL design supports multiple integer and noninteger frequency multiplication factors for both the processor clock and an L2 cache clock. The fully differential delay-interpolating voltage-controlled oscillator (VCO) is tunable over a frequency range determined by programmable frequency limit settings, enhancing yield and application flexibility. PLL lock range for the maximum VCO frequency range settings is 340-612 MHz. The charge-pump current is programmable for additional control of the PLL loop dynamics. A differential on-chip loop filter with common-mode correction improves noise rejection. Cycle-cycle jitter measurements with the microprocessor actively executing instructions were 10.0 ps rms, 80 ps peak to peak (P-P) measured from the clock tree. Cycle-cycle jitter measured for the processor in a reset state with the clock tree active was 8.4 ps rms, 62 ps P-P. PLL area is 1040/spl times/640 /spl mu/m/sup 2/. Power dissipation is <100 mW.