Equivalence checking of combinational circuits using Boolean expression diagrams

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 18; no. 7; pp. 903 - 917
• Main Authors: Hulgaard, H., Williams, P.F., Andersen, H.R.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.07.1999; Institute of Electrical and Electronics Engineers
• Subjects: Analogies; Application software; Applied sciences; Boolean algebra; Boolean functions; Circuit synthesis; Circuits; Combinational circuits; Computer aided design; Councils; Data structures; Design automation; Design engineering; Design. Technologies. Operation analysis. Testing; Electronics; Exact sciences and technology; Information technology; Integrated circuits; Representations; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Standards development; Boolean expression; Binary decision diagram; Experimental result; Equivalence problem; Verification; Data structure; Computer aided design; Implementation; Optimization; Combinatory circuit
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/43.771175

The combinational logic-level equivalence problem is to determine whether two given combinational circuits implement the same Boolean function. This problem arises in a number of computer-aided design (CAD) applications, for example when checking the correctness of incremental design changes (performed either manually or by a design automation tool). This paper introduces a data structure called Boolean expression diagrams (BEDs) and two algorithms for transforming a BED into a reduced ordered binary decision diagram (OBDD). BEDs are capable of representing any Boolean circuit in linear space and can exploit structural similarities between the two circuits that are compared. These properties make BEDs suitable for verifying the equivalence of combinational circuits. BEDs can be seen as an intermediate representation between circuits (which are compact) and OBDD's (which are canonical). Based on a large number of combinational circuits, we demonstrate that BEDs either outperform or achieve results comparable to both standard OBDD approaches and the techniques specifically developed to exploit structural similarities for efficiently solving the equivalence problem. Due to the simplicity and generality of BEDs, it is to be expected that combining them with other approaches to equivalence checking will be both straightforward and beneficial.