Compatibility of silicon gates with hafnium-based gate dielectrics

Silicon gate compatibility problems with hafnium-based gate dielectrics are reported. It generally can be stated that chemical vapor deposition (CVD) silicon gates using silane deposited directly onto polycrystalline HfO 2 at conventional temperatures (near 620 °C) results in (1) a low density of la...

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Published inMicroelectronic engineering Vol. 69; no. 2; pp. 138 - 144
Main Authors Gilmer, D.C., Hegde, R., Cotton, R., Smith, J., Dip, L., Garcia, R., Dhandapani, V., Triyoso, D., Roan, D., Franke, A., Rai, R., Prabhu, L., Hobbs, C., Grant, J.M., La, L., Samavedam, S., Taylor, B., Tseng, H., Tobin, P.
Format Journal Article
LanguageEnglish
Published Elsevier B.V 01.09.2003
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Summary:Silicon gate compatibility problems with hafnium-based gate dielectrics are reported. It generally can be stated that chemical vapor deposition (CVD) silicon gates using silane deposited directly onto polycrystalline HfO 2 at conventional temperatures (near 620 °C) results in (1) a low density of large inhomogeneous polycrystalline-silicon (poly-Si) grains, (2) electrical properties much worse compared to similar HfO 2 films using metal gates or silicon gates with low temperature deposition. However, depositing conventional CVD poly-Si gates directly onto Al 2O 3-capped, hafnium–silicate-capped, or physical vapor deposition (PVD) silicon-capped HfO 2 resulted in the absence of large inhomogeneous poly-Si grains and well behaved capacitors with leakage reduction greater than 10 3 times compared to the poly-Si/HfO 2 and poly-Si/SiO 2 controls of similar electrical thickness. The two observed adverse phenomena for conventional poly-Si deposited directly on HfO 2 are attributed to a partial reduction of the HfO 2 by the poly-Si deposition ambient. In the first case (1) the partial reduction occurs locally on the HfO 2 surface, forming Hf–Si x bond(s) which act as nucleation points for crystalline silicon growth while in the second case (2) the partial reduction occurs along grain boundaries resulting in electrical traps that increase film leakage. In addition, it is postulated that similar adverse interactions with conventionally deposited CVD poly-Si may occur with any transition metal oxide whose metal can form stable silicides.
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ISSN:0167-9317
1873-5568
DOI:10.1016/S0167-9317(03)00290-9