A new family of semidynamic and dynamic flip-flops with embedded logic for high-performance processors

In an attempt to reduce the pipeline overhead, a new family of edge-triggered flip-flops has been developed. The flip-flops belong to a class of semidynamic and dynamic circuits that can interface to both static and dynamic circuits. The main features of the basic design are short latency, small clo...

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Bibliographic Details
Published inIEEE journal of solid-state circuits Vol. 34; no. 5; pp. 712 - 716
Main Authors Klass, F., Amir, C., Das, A., Aingaran, K., Truong, C., Wang, R., Mehta, A., Heald, R., Yee, G.
Format Journal Article
LanguageEnglish
Published IEEE 01.05.1999
Subjects
Circuits
Clocks
Delay
Dynamics
Flip-flops
Latches
Logic
Logic functions
Logic gates
Microprocessors
Pipeline processing
Pipelines
Synchronization
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Summary:In an attempt to reduce the pipeline overhead, a new family of edge-triggered flip-flops has been developed. The flip-flops belong to a class of semidynamic and dynamic circuits that can interface to both static and dynamic circuits. The main features of the basic design are short latency, small clock load, small area, and a single-phase clock scheme. Furthermore, the flip-flop family has the capability of easily incorporating logic functions with a small delay penalty. This feature greatly reduces the pipeline overhead, since each flip-flop can be viewed as a special logic gate that serves as a synchronization element as well.
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ISSN:0018-9200
1558-173X
DOI:10.1109/4.760383