Parallel simulation of ATM switches using relaxation

Algorithms for simulating an ATM switch on a number of parallel processors are described. These include parallel generation and merging of bursty arrival sources, marking and deleting of lost cells due to buffer overflows, and, in one version of the algorithm, computation of departure instants. When...

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Bibliographic Details
Published inPerformance evaluation Vol. 41; no. 2; pp. 149 - 164
Main Authors McGough, A.S, Mitrani, I
Format Journal Article
LanguageEnglish
Published Elsevier B.V 2000
Subjects
ATM networks
Buffer overflow
Parallel prefix
Parallel simulation
Parallel simulation
Buffer overflow
Parallel prefix
ATM networks
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Summary:Algorithms for simulating an ATM switch on a number of parallel processors are described. These include parallel generation and merging of bursty arrival sources, marking and deleting of lost cells due to buffer overflows, and, in one version of the algorithm, computation of departure instants. When the number of lost cells is relatively small, the run time of the simulation is approximately O( N/ P), where N is the total number of cells simulated and P the number of processors. The cells are processed in batches of fixed size; that size affects both the structure and the performance of the algorithms.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
ISSN:0166-5316
1872-745X
DOI:10.1016/S0166-5316(00)00007-9