IBEX: Versatile Readout ASIC With Spectral Imaging Capability and High Count Rate Capability

• Published in: IEEE transactions on nuclear science Vol. 65; no. 6; pp. 1285 - 1291
• Main Authors: Bochenek, M., Bottinelli, S., Broennimann, Ch, Livi, P., Loeliger, T., Radicci, V., Schnyder, R., Zambon, P.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.06.2018; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Acidity; Application specific integrated circuits; Application-specific integrated circuits (ASIC); Calibration; CMOS; CMOS integrated circuits; Comparators; Computer architecture; Counting; Data buses; Data processing; Detectors; Digital to analog conversion; Digital to analog converters; Energy; Energy conservation; energy resolution; high-resolution imaging; Integrated circuits; Overflow; Photonics; Pixels; Power supplies; Radiation; Registers; Semiconductors; Sodium channels; Technology; Thresholds; Transistors; X-ray detectors
• ISSN: 0018-9499; 1558-1578
• DOI: 10.1109/TNS.2018.2832464

IBEX is a novel mixed-mode CMOS application-specific integrated circuit (ASIC), developed at DECTRIS Ltd., dedicated to the readout of hybrid photon counting semiconductor pixel detectors. The chip has been strictly designed in a radiation tolerant enclosed transistor layout and is fabricated in a 110-nm CMOS technology with eight metal layers. It consists of a <inline-formula> <tex-math notation="LaTeX">256\times 256 </tex-math></inline-formula> matrix of <inline-formula> <tex-math notation="LaTeX">75\times 75\,\,\mu \text {m}^{2} </tex-math></inline-formula> pixels, which results in an overall chip size of <inline-formula> <tex-math notation="LaTeX">19.27\times 19.76 </tex-math></inline-formula> mm 2 with periphery, supply, and I/O pads included. A so-called merging mode allows for an increased pixel size of <inline-formula> <tex-math notation="LaTeX">150\times 150\,\,\mu \text {m}^{2} </tex-math></inline-formula>. The pixel readout electronics supports electrons and holes collection, and consists of a charge sensitive preamplifier with programmable gain, a shaper, and two comparators that allow for two independent energy thresholds. In the merging mode, the number of energy thresholds is increased up to four. In order to minimize the pixel-to-pixel energy threshold variation, each pixel comparator can be adjusted with a 6-bit trim digital-to-analog converter. The ASIC can operate in a continuous readout mode with two independent 16-bit counters or in a high counting range mode with a single 32-bit counter per energy threshold level. The chip features counter overflow handling and an instant retrigger technology with an adjustable retrigger time for a significantly improved high-rate counting performance. The ASIC offers a selectable external data bus width of 4, 8, or 16-bit. The count rate limit of the readout chip dc-coupled with a silicon sensor lies at around 10 Mcts/s/pix. The measurements show an electronic pixel noise of <inline-formula> <tex-math notation="LaTeX">89\,\,e^{-} </tex-math></inline-formula>rms and the detectable photon energy range between 3 and 160 keV.